The present invention relates to the bitline precharge circuit of a multi-sectional memory array, which improves the operating speed and also stabilizes the charge equalization operation in the multi-sectional type static RAM.
In designing the large-integrated Memory devices, the design technique of the multi-sectional memory array has been utilized and generalized to gain the operating speed and decrease the operating power consumption. FIG. 1 is a block diagram of the multi-sectional memory array. Therein the cell array is constituted by N sections(S.sub.1 -S.sub.n) and the section is selected or not selected according to the transition of a section decoding signal(SS.sub.L), which is controlled by a section decoder(SD) corresponding to each section.
Also, the section word line(WLS) of each section(S.sub.1 -S.sub.n) is operated by the combination of the main word line(WLM) and the section decoding signal(SS.sub.L). And the bit line precharge part(BP) is operated by the section bit line precharge pulse(.phi..sub.BLS) which is the combination of the section decoding signal(SS.sub.L) and the main bit line precharge pulse(.phi..sub.BLM).
FIG. 3 is a block diagram of the circuit generating the main signals used in FIG. 1. Therein the external address signal(XAk) enters to a row address buffer(RAB) and a short pulse generator(SPG.sub.1), the external address signal(ZAj) enters to a section address buffer(SAB) and a short pulse generator(SPG.sub.2), and the external address signal(YA.sub.i) enters to a column address buffer(CAB) and a short pulse generator(SPG.sub.3).
The output of the row address buffer(RAB) and the output of the section address buffer(SAB) are combined to generate the main word line(WLM) and the section decoding signal(SS.sub.L) through a row predecoder and decoder(RPD) and a section predecoder and decoder(SPD), respectively. A column predecoder and decoder(CPD) receives the output of the column address buffer(CAB) and generates the column decoding signal(CD.sub.i) to select a bit line. On the other hand, a .phi..sub.PX pulse generator(G.sub.1) receives the outputs(SPG.sub.k, SPG.sub.j) of the short pulse generator(SPG.sub.1, SPG.sub.2) and generates a .phi..sub.PX pulse, and a .phi..sub.PY pulse generator(G.sub.2) receives the output(SPG.sub.i) of the short pulse generator(SPG.sub.3) and generates a .phi..sub.PY pulse.
Finally, the .phi..sub.PX pulse generates to the main bit line precharge pulse (.phi..sub.BLM) by passing through two invertors (I.sub.10, I.sub.11) and, the .phi..sub.PX pulse and the .phi..sub.PY pulse are greatly combined by passing (.phi..sub.DLM) through a NOR gate(NO.sub.10) and a delay circuit(DY.sub.10) to generate then main dataline circuit (DY.sub.10).
FIG. 2 is a circuit diagram of the conventional multi-sectional memory array, which embodies the previously described FIG. 1.
Referring to FIG. 6, the precharge operation of the circuit is as follows:
Assume that a new section is going to be accessed with a new combination of input addresses.
First, the address transition generates short pulses(SPG.sub.k, SPG.sub.j, SPG.sub.i) at SPG.sub.1 or SPG.sub.2 or SPG.sub.3.
Soon after, the short pulses generate to the main precharge pulses .phi..sub.BLM, .phi..sub.DLM. On the other hand, the new combination of address inputs result in a new section decoding output.
A time, t.sub.1, is defined as the delay time from the address inputs to the new output of section decoding circuit and a time, mt.sub.1, is defined as the spare time from the new output of section decoding circuit to the main bit line precharge pulse, .phi..sub.BLM.
The new section is selected by section decoding signal(SS.sub.L), then main bit line and data line precharge pulses(.phi..sub.BLM, .phi..sub.DLM) appear, so the charge and equalization are attained by the driving transistors(TP.sub.1 -TP.sub.6) of FIG. 2. At this time the bit line has been partially charged by the transistors(TN.sub.1, TN.sub.2) in the non-selected condition, however since the transistors are usually designed to have a very small size due to read speed and operation current, the charging of the bit line by the transistors is very slow and is thus substantially negligible. Thus the said section decoding signal(SS.sub.L) should respond within the shortest time from the address input and precedes the leading edge of the main bit line and data line precharge pulse(.phi..sub.BLM, .phi..sub.DLM) with the spare time(mt.sub.1), to guarantee enough precharge time of bit lines and data lines. In the case where mt.sub.1 &lt;0, depending on the surroundings, the pulse width of the said section bit line and data line precharge pulse(.phi..sub.BLS, .phi..sub.DLS) decreases and it is difficult to sufficiently precharge the section bit line(BLS) and the section data line(DLS), so careful attention must be paid when the chip is designed. Thus, there is a problem due to the operation speed of the whole chip being limited by the section decoding signal(SS.sub.L) which selects or deselects the section and the operation itself is unstable in certain instances.